Analog/Mixed-Signal Circuit Design Engineer

Key Responsibilities:

• Design, simulate, and optimize full-custom analog circuits for high-performance interface IPs

• Perform circuit design, verification, and characterization across process, voltage, and temperature corners

• Develop and validate analog building blocks such as:

  • PLLs

  • Front-end amplifiers

  • CTLE/DFE equalization circuits

  • SerDes-related analog circuits

  • ESD and latch-up protection structures

• Conduct transistor-level simulation and post-layout verification to ensure performance, robustness, and manufacturability

• Collaborate closely with layout, digital, system, and verification teams throughout the design cycle

• Support silicon bring-up, lab validation, and performance characterization when required

• Contribute to IP development targeting advanced technology nodes from 28nm to 6nm and beyond

Technical Areas / IPs You Will Work On:

The candidate will contribute to analog and mixed-signal IP development for a range of industry-standard interfaces, including:

Serial/Parallel communication interfaces

• PCIe

• USB

• SATA

• DDR

• LPDDR

• UCIe

• ONFI
  

Display interfaces

• DisplayPort

• HDMI

• V-by-One (Vx1)

• eDP
  

Qualifications:

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Microelectronics, or related field

• Solid knowledge or design experience in one or more of the following:

  • PLL design

  • Front-end amplifier design

  • CTLE/DFE design

  • General SerDes design

  • ESD/latch-up design and reliability considerations

• Strong understanding of analog and mixed-signal circuit fundamentals

• Experience with transistor-level simulation, circuit characterization, and silicon correlation

• Familiarity with advanced CMOS technology nodes, ideally from 28nm down to 6nm

• Good problem-solving skills and the ability to work effectively in cross-functional teams
  

Preferred Qualifications:

• Experience in high-speed interface IP development

• Knowledge of signal integrity, equalization, and high-speed link design

• Experience with post-silicon validation and debugging

• Familiarity with reliability design considerations in advanced nodes